Map / Chip factories and packaging
TSMC TSM
Makes nearly every leading AI accelerator and runs CoWoS, the dominant AI chip packaging line.
Chokepoints it holds
Depends on
- ASML: EUV lithography. Taiwan took 30% of ASML's Q2 2026 machine shipments. Investing.com, 2026-07-15
- Applied Materials: Deposition and packaging tools. Q4 FY26 revenue guide about $10.3B, driven by AI logic and memory. BigGo Finance, 2026-08-14 Our inference
Supplies
- Nvidia: Blackwell and Rubin chips. Analysts estimate Nvidia passed Apple as TSMC's largest customer in 2026, about 22% of revenue. MacRumors, 2026-01-28
- Nvidia: CoWoS packaging capacity. Nvidia reportedly holds more than half of TSMC's 2026 CoWoS capacity. TrendForce, 2026-08-05
- AMD: 2nm server CPUs and MI455X. AMD Venice is the first x86 server CPU on TSMC 2nm. Moor Insights & Strategy, 2026-07-24
- Broadcom: Custom AI chips on 3nm. Google's TPU v7 is made on TSMC 3nm; Meta's MTIA is reportedly moving to 3nm. Tom's Hardware, 2026-05
- Google (Alphabet): 8th-generation TPUs on 2nm. Both 8th-gen TPU variants target late 2027 on TSMC 2nm. The Next Web, 2026-04-22
- ASE / SPIL: Outsourced CoWoS front-end step. TSMC reportedly outsources the chip-on-wafer step to ASE. TrendForce, 2026-08-05
Data as of 2026-10-01. Cite as: Ye, Mike. "TSMC" (tsmc). AI Lattice, dataset v0.1.0. https://ailattice.ai/e/tsmc/. How to cite.