Map / Chip factories and packaging
ASE / SPIL ASX
Largest outside packaging house; now taking part of TSMC's CoWoS work.
Chokepoints it holds
Depends on
- TSMC: Outsourced CoWoS front-end step. TSMC reportedly outsources the chip-on-wafer step to ASE. TrendForce, 2026-08-05
Supplies
- AMD: Packaging capacity. AMD providing strategic backing to ASE and SPIL capacity. TrendForce, 2026-08-05
Data as of 2026-10-01. Cite as: Ye, Mike. "ASE / SPIL" (ase). AI Lattice, dataset v0.1.0. https://ailattice.ai/e/ase/. How to cite.